On 02/10/15 08:20, Adrien Prost-Boucle wrote:
Hi,
Just curious, how to exit such a recursion? if-generate does not have an
else-clause, IIRC.
The classic implementation is like that:
if <recurs-condition> generate
<recursive instantiation>
end generate;
if not <recurs-condition> generate
<end of recursion>
end generate;
I think the else statement now exists in VHDL-2008,
but we shouldn't expect that VHDL version > 93 are supported by synthes
is tools...
BTW I have a question:
when writing an entity that does recursive instantiation, I have to
declare the current entity as component in architecture.
This re-declaration seems completely useless to me, is it required by
the VHDL standard?
The bug is in GHDL: it will certainly crash if you instantiate the
entity directly.
Tristan.
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