On 09/03/16 21:37, Adrien Prost-Boucle wrote:
Hi,
I have a VHDL design that GHDL simulates at a speed of only one or 2
clock cycles per second. The same design, same VHDL files, is simulated
by Xilinx Vivado 2015.3 at a speed of 400 clock cycles per second.
For all other designs I have and/or generate, GHDL is always noticeably
faster that Vivado, so I think my current app exhibits a GHDL behaviour
that at least could be improved.
Note that the attached VHDL was generated by a HLS tool so it's not
easy to read... and unfortunately I can't reduce the VHDL code to
something simpler that exhibits the slowdown.
The top-level entity is the testbench entity "tb". The simulation is
supposed to stop after around 550k clock cycles.
The slowdown is very visible. As suggested by David, this could be due
to a memory leak. I will investigate.
Thanks,
Tristan.
_______________________________________________
Ghdl-discuss mailing list
Ghdl-discuss@gna.org
https://mail.gna.org/listinfo/ghdl-discuss
