On 05/10/16 20:25, Patrick Lehmann wrote:
Hello,
I think, if an interface is required, it should export a DOM not the
AST. ASTs are parser specific and hard to read. I don't know the AST of
GHDL, but I had to use other ASTs which needed a lot of work to
read/parse them.
The lately announced pyVHDLParser has a VHDL DOM (Document Object
Model). This model is fixed for VHDL-2008 and does not depend on the
parser. So other parsers could generate the same model. It's simple to
translate this model to Ada or C.
A DOM doesn't containt resolve names or types, it's a compact in-memory
representation of a single VHDL file. It comes with methods to find
information like GetObjectOfLabel("baz").
document
o- entity
o- name: "foo"
o- libraries
o- "ieee"
o- uses
o- "ieee.std_logic_1164.all"
o- "ieee.numeric_std.all"
o- ports
o- port
o- name: "clk"
o- type: "std_logic"
o- architecture
o- name: "rtl"
o- entity: "foo"
o- libraries
o- uses
o- declared-items
o- constant
o- name: "bar"
o- type: "integer"
o- init-value: 5
This could also be exported as XML, JSON, ...
My model for pyVHDLParser is still in development, but one can look into
the code and get an impression of a DOM:
https://github.com/Paebbels/pyVHDLParser/blob/master/pyVHDLParser/Model/VHDLModel.py
Sorry I have no picture available, but running the Frontend.py with
simple_1.vhdl in mode 32 would present a first translation into the
mentioned DOM :).
Such a DOM could already be useful for many applications, but most of
the emails here demand for a complete design model ...
It should also be possible to generate a resolved model. So multiple
files are combined, symbols are resolved, constants are propagated and
e.g. unused generate statements are removed. I hope I can show results
for that design model in a few weeks :).
@Tristan: Has GHDL such a DOM? How complex is it to translate the
internal structure to such a DOM?
If you look at disp_vhdl, this module is able to reprint vhdl sources
from the AST. So generating the above DOM shouldn't be very difficult.
Tristan.
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