Hi Carlos, Here is how I compiled the Xilinx Corelib and Unisim Lib a while ago: https://cervisial.wordpress.com/2016/01/11/using-the-xilinx-unisim-and-xilinxcorelib-with-ghdl-on-mac-osx/
I did that on my Mac, but same should be valid on Linux. Am Montag, 24. Oktober 2016 schrieb Carlos Alberto Ruiz : > > Hello, > > I am having problems with xilinxcorelib, I use ISE: > > /usr/local/bin/ghdl -a --workdir=/home/cruiz/ELINT/ > 95512010_FPGA_central/tsb/global/vunit_out/ghdl/libraries/xilinxcorelib > --work=xilinxcorelib --std=08 -P/home/cruiz/ELINT/95512010_ > FPGA_central/tsb/global/vunit_out/ghdl/libraries/vunit_lib > -P/home/cruiz/ELINT/95512010_FPGA_central/tsb/global/vunit_ > out/ghdl/libraries/xilinxcorelib --ieee=synopsys -frelaxed-rules > --no-vital-checks --std=93c -fexplicit /opt/Xilinx/14.7/ISE_DS/ISE/ > vhdl/src/XilinxCoreLib/convolution_legacy_v8_0.vhd > > > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/fir_compiler_v5_0_sim_comps.vhd into xilinxcorelib ... > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/dds_compiler_v5_0_xst_comp.vhd into xilinxcorelib ... > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/dds_compiler_v4_0_xst_comp.vhd into xilinxcorelib ... > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/dds_compiler_v4_0_comp.vhd into xilinxcorelib ... > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/convolution_v6_1.vhd into xilinxcorelib ... > Compiling ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/convolution_legacy_v8_0.vhd into xilinxcorelib ... > /opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/XilinxCoreLib/ > convolution_legacy_v8_0.vhd:58:113: unit "bip_utils_pkg_v2_0" not found > in library "xilinxcorelib" > Failed to compile ../../../../../../opt/Xilinx/14.7/ISE_DS/ISE/vhdl/src/ > XilinxCoreLib/convolution_legacy_v8_0.vhd with command: > /usr/local/bin/ghdl -a --workdir=/home/cruiz/ELINT/ > 95512010_FPGA_central/tsb/global/vunit_out/ghdl/libraries/xilinxcorelib > --work=xilinxcorelib --std=08 -P/home/cruiz/ELINT/95512010_ > FPGA_central/tsb/global/vunit_out/ghdl/libraries/vunit_lib > -P/home/cruiz/ELINT/95512010_FPGA_central/tsb/global/vunit_ > out/ghdl/libraries/xilinxcorelib --ieee=synopsys -frelaxed-rules > --no-vital-checks --std=93c -fexplicit /opt/Xilinx/14.7/ISE_DS/ISE/ > vhdl/src/XilinxCoreLib/convolution_legacy_v8_0.vhd > > > Does anyone know what could be the problem? > > Thank you. > > > -- > > > > > > *Carlos Alberto Ruiz Naranjo* > *FPGA engineer* > cr...@dasphotonics.com > <javascript:_e(%7B%7D,'cvml','cr...@dasphotonics.com');> > > > > > *DAS Photonics S.L. Ciudad Politécnica de la Innovación, Camino de Vera > s/n.Acceso K, Edificio 8F, 2ª planta 46022 Valencia - SPAINTelf: +34 963 > 556 150 - Directo: +34 --------------* > > > > > *www.dasphotonics.com <http://www.dasphotonics.com/> Before printing this > email think well whether it is really necessary.This e-mail contains > confidential information.It is for the intended recipient only. If you are > not the intended recipient of this e-mail, please notify the author by > replying to this e-mail immediately and delete the message from your > computer. If you are not the intended recipient you must not use, disclose, > distribute, copy, print or rely on this e-mail* > > >
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