Hi all,
First my congrats for this tool that i just discovered : huge !

I experimented an issue with signals of type 'real' :

consider the following simple test bench :


*library std;**
**   use std.textio.all;**
**
**     entity real_array is**
**     end real_array;**
****
**     architecture behav of real_array is**
****
**        signal r1 , r2 : real := 0.1;**
**        signal i1 , i2 : integer := 0;**
**     begin**
****
**        process**
**           variable line_v   : line;**
**          file     out_file : text open write_mode is "out.txt";**
****
**           type real_array is array (natural range <>) of real;**
**           constant real_tab : real_array := (1.0,5.0 , 10.0, 100.0);**
****
**        begin**
**           --  Check each pattern.**
**           for i in real_tab'range loop**
**              r1 <= real_tab(i mod 4);**
**              r2 <= r1*r1;**
**              i1 <= integer(r1);**
**              i2 <= integer(r2);**
****
**              write(line_v, i);**
**              write(line_v, string'(" "));**
**              write(line_v, r1);**
**              write(line_v, string'(" "));**
**              write(line_v, r2);**
**              write(line_v, string'(" "));**
**              writeline(out_file, line_v);**
****
**              wait for 1 ns;**
**              --  Check the outputs.**
**              assert r1 < 1000.0**
**                 report "bad r1 high value" severity note;**
**              assert r1 > 1.0e-5**
**                 report "bad r1 low value" severity note;**
****
**           end loop;**
**           assert false report "end of test" severity note;**
**           --  Wait forever; this will finish the simulation.**
**           wait;**
**        end process;**
**     end behav;*

when i execute it with *ghdl -r real_array  --vcd=real_array.vcd : *
execution is fine, no error and output is as expected   :

0 1.0e-1 1.0e-1
1 1.0e0 1.0e-2
2 5.0e0 1.0e0
3 1.0e1 2.5e1

but when i look the wave form with gtkwave, some values of real signals are wrong the issue is inside the generated VCD file (i added the comments OK / not OK for the real signals )


$date
  Fri Mar 24 07:23:42 2017
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$var real 64 ! r1 $end
$var real 64 " r2 $end
$var integer 32 # i1 $end
$var integer 32 $ i2 $end
$enddefinitions $end
#0
r1.00000E000 !   OK
r1.00000E-002 " OK
b0 #
b0 $
#1000000
r5.00000E000 !  OK
r1.00000E000 " OK
b1 #
#2000000
r:.00000E000 ! NOK
r2.50000E001 " OK
b101 #
b1 $
#3000000
r:.00000E001 ! NOK ???
r:.00000E001 " NOK ???
b1010 #
b11001 $
#4000000



Any idea ?
the storage of real in VCD seems to fail sometimes
Regards
pm


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