Gitweb:     
http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=64a8170975947978ea4094dd6c4b1f41119d6ae6
Commit:     64a8170975947978ea4094dd6c4b1f41119d6ae6
Parent:     5c8d52015c09b42632a73896f8a80cff64c5c1d1
Author:     Alan Cox <[EMAIL PROTECTED]>
AuthorDate: Tue Jul 24 15:17:48 2007 +0100
Committer:  Jeff Garzik <[EMAIL PROTECTED]>
CommitDate: Tue Jul 24 16:55:02 2007 -0400

    pata_hpt37x: Fix 2.6.22 clock PLL regression
    
        Just one version of Linux ago
        The PLL code broke - oh no!
        But set the right mode
        And fix up the code
        Makes the PLL timing sync go
    
    [whatever happened to the sailor from Nantucket, hero of many limericks?  
-jg]
    
    Closes-bug: #8791
    Signed-off-by: Alan Cox <[EMAIL PROTECTED]>
    Signed-off-by: Jeff Garzik <[EMAIL PROTECTED]>
---
 drivers/ata/pata_hpt37x.c |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/ata/pata_hpt37x.c b/drivers/ata/pata_hpt37x.c
index b0af65a..84d9c55 100644
--- a/drivers/ata/pata_hpt37x.c
+++ b/drivers/ata/pata_hpt37x.c
@@ -26,7 +26,7 @@
 #include <linux/libata.h>
 
 #define DRV_NAME       "pata_hpt37x"
-#define DRV_VERSION    "0.6.6"
+#define DRV_VERSION    "0.6.7"
 
 struct hpt_clock {
        u8      xfer_speed;
@@ -1103,17 +1103,17 @@ static int hpt37x_init_one(struct pci_dev *dev, const 
struct pci_device_id *id)
 
                /* Select the DPLL clock. */
                pci_write_config_byte(dev, 0x5b, 0x21);
-               pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
+               pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 
0x100);
 
                for(adjust = 0; adjust < 8; adjust++) {
                        if (hpt37x_calibrate_dpll(dev))
                                break;
                        /* See if it'll settle at a fractionally different 
clock */
-                       if ((adjust & 3) == 3) {
-                               f_low --;
-                               f_high ++;
-                       }
-                       pci_write_config_dword(dev, 0x5C, (f_high << 16) | 
f_low);
+                       if (adjust & 1)
+                               f_low -= adjust >> 1;
+                       else
+                               f_high += adjust >> 1;
+                       pci_write_config_dword(dev, 0x5C, (f_high << 16) | 
f_low | 0x100);
                }
                if (adjust == 8) {
                        printk(KERN_WARNING "hpt37x: DPLL did not 
stabilize.\n");
-
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