Fixes #4072 (re: `my_module inst (d, q);` creating tags for both the instance `inst` and the module `my_module`). The unit tests have been updated accordingly.
Also includes a minor amendment to #4039 to fix the tag grouping for SystemVerilog so that enum objects are put in the same group as struct/union objects, which makes more sense than putting them in the same group as typedefs (which are types, not objects). You can view, comment on, or merge this pull request online at: https://github.com/geany/geany/pull/4075 -- Commit Summary -- * Change icon of SystemVerilog struct/enum objects * tagmanager: Verilog: don't tag module of instances -- File Changes -- M src/tagmanager/tm_parser.c (7) M tests/ctags/sysverilog.sv (4) M tests/ctags/sysverilog.sv.tags (4) -- Patch Links -- https://github.com/geany/geany/pull/4075.patch https://github.com/geany/geany/pull/4075.diff -- Reply to this email directly or view it on GitHub: https://github.com/geany/geany/pull/4075 You are receiving this because you are subscribed to this thread. Message ID: <geany/geany/pull/[email protected]>
