tustvold commented on code in PR #6155:
URL: https://github.com/apache/arrow-rs/pull/6155#discussion_r1715245167
##########
arrow-buffer/src/buffer/null.rs:
##########
@@ -131,9 +176,20 @@ impl NullBuffer {
}
/// Returns the null count for this [`NullBuffer`]
- #[inline]
pub fn null_count(&self) -> usize {
- self.null_count
+ match &self.null_count {
+ NullCount::Eager(v) => *v,
+ NullCount::Lazy(v) => {
+ let cached_null_count = v.load(Ordering::Acquire);
+ if cached_null_count != UNINITIALIZED_NULL_COUNT {
+ return cached_null_count as usize;
+ }
+
+ let computed_null_count = self.buffer.len() -
self.buffer.count_set_bits();
+ v.store(computed_null_count as i64, Ordering::Release);
Review Comment:
No, all processors have coherent caches. You can't observe two different
values for the same memory locations simultaneously. The ordering concerns
whether operations performed to other memory locations are guaranteed to be
visible following this operation
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