Add RDHWR-based cycle counter module for MIPS32R2.
OS must enable CC/CCRes bits for user-mode RDHWR to work so the
code path is available on Linux only for now. NetBSD should be
usable as well though.
MIPS32R6 is omitted (though certainly compatible) as no testing
was performed there.
v2 limits the counter to linux as per mailing list discussion.
diff -r 7423efa39db8 -r dcd5adde7731 configure.ac
--- a/configure.ac
+++ b/configure.ac
@@ -1057,6 +1057,12 @@
esac
;;
+ mipsisa32r2*-*-linux*)
+ SPEED_CYCLECOUNTER_OBJ=mips32r2.lo
+ cyclecounter_size=1
+ path="mips32/r1 mips32"
+ ;;
+
mipsisa32*-*-*)
path="mips32/r1 mips32"
;;
diff -r 7423efa39db8 -r dcd5adde7731 tune/Makefile.am
--- a/tune/Makefile.am
+++ b/tune/Makefile.am
@@ -33,7 +33,7 @@
AM_LDFLAGS = -no-install
EXTRA_DIST = alpha.asm pentium.asm sparcv9.asm hppa.asm hppa2.asm hppa2w.asm \
- ia64.asm powerpc.asm powerpc64.asm x86_64.asm many.pl
+ ia64.asm powerpc.asm powerpc64.asm x86_64.asm mips32r2.asm many.pl
noinst_HEADERS = speed.h
# Prefer -static on the speed and tune programs, since that can avoid
diff -r 7423efa39db8 -r dcd5adde7731 tune/mips32r2.asm
--- /dev/null
+++ b/tune/mips32r2.asm
@@ -0,0 +1,12 @@
+include(`../config.m4')
+
+ASM_START()
+PROLOGUE(speed_cyclecounter)
+ rdhwr $2,$2
+ slti $3,$2,0
+ sll $2,$2,1 C save multiply and assume CCRes is 2
+ sw $3,4($4)
+ jr $ra
+ sw $2,0($4)
+EPILOGUE(speed_cyclecounter)
+ASM_END()
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