Felix" > On Sun, Apr 03, 2022 at 01:14:57PM +0200, k...@aspodata.se wrote: > > How do I conert a sym file to verilog ? > > > > My conclusion is that it isn't meaningful to do automatic conversion > > from sym file to verilog-ams file except perhaps for a first skeleton > > containing the port names used. > > > > And for a first skeleton, should a converter use the pinseq, pinnumber > > or the pinlabel attribute for the ports ? > > It's much the same as schematics. geda has top level objects, and > verilog doesn't, so you put everything into a module definition. The > goal is to reproduce the sym file back from its verilog representation > (round-trip). ...
I think we talk about differt things. I pose the question: given a sym file, what content should the verilog-ams conversion have You talk about the gnucap-geda code, we should have a differnt thread for that. Regards, /Karl Hammar
