On Tue, Jun 22, 2010 at 6:45 PM, Glenn Brown <gl...@myri.com> wrote:
> +/*
> + * Initialize NonVolatile storage support for a device.
> + *
> + * @v priv Device private data for the device.
> + * @ret rc 0 on success, else an error code.
> + */
> +
> +static int myri10ge_nv_init ( struct myri10ge_private *priv )
> +{
> + int rc;
> + struct myri10ge_eeprom_header
> + {
> + uint8 __jump[8];
> + uint32 eeprom_len;
> + uint32 eeprom_segment_len;
> + uint32 mcp1_offset;
> + uint32 mcp2_offset;
> + uint32 version;
> + } hdr;
> + uint32 mcp2_len;
> + unsigned int nvo_fragment_pos;
> +
> + DBGP ( "myri10ge_nv_init\n" );
> +
> + /* Read the EEPROM header, and byteswap the fields we will use.
> + This is safe even though priv->nvs is not yet initialized. */
> +
> + rc = myri10ge_nvs_read ( &priv->nvs, 0, &hdr, sizeof ( hdr ) );
> + if ( rc ) {
> + DBG ( "EEPROM header unreadable\n" );
> + return rc;
> + }
> + hdr.eeprom_len = bswap_32 ( hdr.eeprom_len );
> + hdr.eeprom_segment_len = bswap_32 ( hdr.eeprom_segment_len );
> + hdr.mcp2_offset = bswap_32 ( hdr.mcp2_offset );
> + hdr.version = bswap_32 ( hdr.version );
Does be32_to_cpu() make sense instead of bswap_32()? It would be nice not to
assume a little-endian CPU. There is another bswap_32() a few lines down.
> + DBG2 ( "eelen:%xh seglen:%xh m...@%xh ver%d\n", hdr.eeprom_len,
> + hdr.eeprom_segment_len, hdr.mcp2_offset, hdr.version );
> +
> + /* If the firmware does not support EEPROM writes, simply return. */
> +
> + if ( hdr.version < 1 ) {
> + DBG ( "No EEPROM write support\n" );
> + return 0;
> + }
> +
> + /* Read the length of MCP2. */
> +
> + rc = myri10ge_nvs_read ( &priv->nvs, hdr.mcp2_offset, &mcp2_len, 4 );
> + mcp2_len = bswap_32 ( mcp2_len );
Stefan
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