On Wed 16 May 2012 06:23, Mark H Weaver <m...@netris.org> writes: > It's surprising to me for another reason: in order to make the > instructions reasonably compact, only a limited number of bits are > available in each instruction to specify which registers to use.
It turns out that being reasonably compact isn't terribly important -- more important is the number of opcodes it takes to get something done, which translates to the number of dispatches. Have you seen the "direct threading" VM implementation strategy? In that case the opcode is not an index into a jump table, it's a word that encodes the pointer directly. So it's a word wide, just for the opcode. That's what JavaScriptCore does, for example. The opcode is a word wide, and each operand is a word as well. The design of the wip-rtl VM is to allow 16M registers (24-bit addressing). However many instructions can just address 2**8 registers (8-bit addressing) or 2**12 registers (12-bit addressing). We will reserve registers 253 to 255 as temporaries. If you have so many registers as to need more than that, then you have to shuffle operands down into the temporaries. That's the plan, anyway. Cheers, Andy -- http://wingolog.org/
