Hi Shea, sorry for the delay. Shea Levy <[email protected]> writes: > * module/system/base/target.scm (cpu-endianness): Add case for "riscv" > variants.
Applied in commit 08bb4628369cf3efe7c96a32919705c41a9ed9e9 of the
stable-2.2 branch, so it will be included in Guile-2.2.4.
Thank you for working on RISC-V. That project gives me hope :)
Mark
