guix_mirror_bot pushed a commit to branch master
in repository guix.
commit 1adf50f5df549109725734c12b202d2aa1453601
Author: Danny Milosavljevic <[email protected]>
AuthorDate: Thu Jan 1 21:10:54 2026 +0100
gnu: Add python-hdlconvertorast.
* gnu/packages/electronics.scm (python-hdlconvertorast): New variable.
---
gnu/packages/electronics.scm | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm
index fe8da9dd42..efac568cff 100644
--- a/gnu/packages/electronics.scm
+++ b/gnu/packages/electronics.scm
@@ -2179,6 +2179,32 @@ a standard file format used in @acronym{EDA, Electronic
Design Automation}
for example for timing information of digital circuits.")
(license license:gpl3+)))
+(define-public python-hdlconvertorast
+ (package
+ (name "python-hdlconvertorast")
+ (version "1.2")
+ (source
+ (origin
+ (method git-fetch)
+ (uri (git-reference
+ (url "https://github.com/Nic30/hdlConvertorAst";)
+ (commit (string-append "v" version))))
+ (file-name (git-file-name name version))
+ (sha256
+ (base32 "1zv067imbdihyqwy7f0j80x9a2857vifhky60vc91dffjl1zjg1i"))))
+ (build-system pyproject-build-system)
+ (native-inputs
+ (list python-pytest
+ python-setuptools))
+ (home-page "https://github.com/Nic30/hdlConvertorAst";)
+ (synopsis "@acronym{AST, Abstract Syntax Tree} library for VHDL and
+SystemVerilog")
+ (description
+ "This package provides a library of @acronym{AST, Abstract Syntax Tree}
nodes
+for @acronym{VHDL, Very high speed integrated circuit Hardware Description
Language},
+SystemVerilog, and SystemC, with conversion between languages and to JSON.")
+ (license license:expat)))
+
(define-public python-pyucis
(package
(name "python-pyucis")
