guix_mirror_bot pushed a commit to branch next-master
in repository guix.
commit 88e5efec9f5e939c207c6da39b0392b9c8fd9873
Author: Cayetano Santos <[email protected]>
AuthorDate: Sat Jan 17 10:55:26 2026 +0100
gnu: iverilog: Update to 20251012.
* gnu/packages/electronics.scm (iverilog): Update to 20251012.
[native-inputs]: Add perl and tcsh.
[synopsis]: Complete.
[description]: Update.
Change-Id: I27ecf7a5366e7e62fe1d4a0f92390384d207f54c
---
gnu/packages/electronics.scm | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/gnu/packages/electronics.scm b/gnu/packages/electronics.scm
index ad16c2bc02..157ba51f9f 100644
--- a/gnu/packages/electronics.scm
+++ b/gnu/packages/electronics.scm
@@ -618,17 +618,17 @@ Simulator Trace} files.")
(define-public iverilog
(package
(name "iverilog")
- (version "12.0")
+ (version "20251012")
(source
(origin
(method git-fetch)
(uri (git-reference
(url "https://github.com/steveicarus/iverilog";)
(commit
- (string-append "v" (string-replace-substring version "."
"_")))))
+ (string-append "s" version))))
(file-name (git-file-name name version))
(sha256
- (base32 "1cm3ksxyyp8ihs0as5c2nk3a0y2db8dmrrw0f9an3sl255smxn17"))))
+ (base32 "05k4x4lcgx554w2a8qcmmgjmg0k6swvcwl1pn5kcv4xafcz6rmxj"))))
(build-system gnu-build-system)
(arguments
(list
@@ -645,17 +645,17 @@ Simulator Trace} files.")
"s;@IVCC@;gcc;")
(("s;@IVCXX@;\\$\\(CXX);")
"s;@IVCXX@;g++;")))))))
- (native-inputs (list autoconf bison flex gperf))
+ (native-inputs (list autoconf bison flex gperf perl tcsh))
(inputs (list zlib))
(home-page "https://steveicarus.github.io/iverilog/";)
- (synopsis "FPGA Verilog simulation and synthesis tool")
+ (synopsis "Verilog/SystemVerilog HDL compiler")
(description
- "Icarus Verilog is a Verilog simulation and synthesis tool.
-It operates as a compiler, compiling source code written in Verilog
-(IEEE-1364) into some target format.
+ "Icarus Verilog is a Verilog/SystemVerilog @acronym{EDA, Electronic
+Design Automation} compiler that generates code employed by back-end
+tools. It operates compiling source code written in Verilog
+(IEEE-1364) and SystemVerilog (IEEE-1800) into some target format.
For batch simulation, the compiler can generate an intermediate form
-called vvp assembly.
-This intermediate form is executed by @command{vvp}.
+called vvp assembly. This intermediate form is executed by @command{vvp}.
For synthesis, the compiler generates netlists in the desired format.")
;; GPL2 only because of:
;; - ./driver/iverilog.man.in
