❦ 23 novembre 2013 10:47 CET, Willy Tarreau <w...@1wt.eu> :
>> > However you must absolutely figure what core shares L2 with what other
>> > core. I suspect you'll have core 0 + core 3, core 1 + core 4, core 2 +
>> > core 5. But that's only a guess.
>>
>> I don't know if this is reliable, but you can have this information in
>> /sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list.
>
> Wow thanks Vincent, that's excellent. I was used to read cpuinfo only
> and to try by hand. That's definitely better this way.
I didn't find the appropriate command when I first posted, but I now
remember that `cpuid` can also output a lot of information when it is
recent enough:
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x0 (0)
extra processor cores on this die = 0x1 (1)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
WBINVD/INVD behavior on lower caches = true
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x0 (0)
extra processor cores on this die = 0x1 (1)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
WBINVD/INVD behavior on lower caches = true
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 63
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
extra threads sharing this cache = 0x1 (1)
extra processor cores on this die = 0x1 (1)
system coherency line size = 0x3f (63)
physical line partitions = 0x0 (0)
ways of associativity = 0x7 (7)
WBINVD/INVD behavior on lower caches = true
inclusive to lower caches = false
complex cache indexing = false
number of sets - 1 (s) = 4095
It's from an early Core 2 Duo (Intel Core 2 Duo (Allendale B2), 65nm). I
am too lazy to check on my laptop which is more recent.
--
Say what you mean, simply and directly.
- The Elements of Programming Style (Kernighan & Plauger)
