On 11/14/06, Robin Garner <[EMAIL PROTECTED]> wrote:
>Whether this helps performance depends on the cache policy of the >multiprocessor. I'm not sufficiently versed in cache architectures to >say, but I would expect that machines with sufficiently weak memory >models will make this cheap, those without will be expensive.
Salikh points out an interesting issue, but I think that this may be subject to some assumptions about SMP and hypertheaded architectures, and prevalent L2 sharing models, at least on certain processors. This is a rapidly changing area and as Weldon points out, the best approach may be to do the prototype, and then run analytical tools to identify the pathologies and tweak accordingly. Upfront, the overhead of a level of indirection, the benefits of sharing the same cache line as the gcmap ptr and the cost of the false sharing on some architectures is diffcult to figure out without prototyping.
