At 10:11 -0500 97/10/29, Benjamin Goldberg wrote:
>Just as a note, the computer architecture folks have designed support
>for speculative execution in the presence of exception-causing
>instructions. The idea, as embodied, for example, in the
>Hewlett-Packard Playdoh architecture, is that there is a speculative
>version of each instruction. The speculative version of the
>instruction behaves indentically to the normal instruction, except
>that if an exceptional condition occurs (such as divide by zero), an
>exception is not raised. Rather, a bit (called the speculative bit) is
>set in the destination register to indicate that the condition
>occurred. If a normal (i.e. non-speculative) instruction ever has an
>operand whose speculative bit is set, then the exception is raised. If
>a speculative instruction encounters an operand register with its speculative
>bit set, the speculative bit on the destination register is set (i.e.
>speculative bits propagate through speculative instructions).
This sounds like a step in the right direction, but I think one should go
all the way, making C++ "zero-overhead" style exception handling moving
down to the CPU level. Is this work on this also being done?
Hans Aberg
* Email: Hans Aberg <mailto:[EMAIL PROTECTED]>
* AMS member listing: <http://www.ams.org/cml/>
