Hi Beniamino, Jan, On 09/29/2013 05:41 PM, Beniamino Galvani wrote: > On Sat, Sep 28, 2013 at 04:35:38PM -0400, Ján Veselý wrote: >> [...] >> I don't know armv6 and the BCM chip on raspberry well enough to have >> definite answers, >> my suspicion is that enabling caches causes incoherent page tables, >> here are few hints you can try. >> >> pt_coherence (page_armv6.h) macro makes sure pagetable information are >> flushed to the Point of Unification (PoU) [0]: >> * you can try changing the pt_coherence macro to flush to the Point >> of Coherence [1] (DCCMVAU -> DCCMVAC, this is probably the easiest) >> * you can try using write-through caches instead of >> writeback-writeallocate[2] (the speedup is noticeable so you should be >> able to tell, see page_armv6.h:259 for info on what to change and how) >> * you can try flushing all caches to PoC before flushing TLB on as switch >> >> if any of the above fixes the issue, it confirms that memory coherence >> is the cause. Note than none of the above is a real fix. >> It might be that I enabled some the necessary actions only for armv7. >> the basic requirements are that info is present in page-walk >> accessible memory (pt_coherence macro), and MMU is allowed to use >> caches for pt-walks (set_ptl0_addr). There might be similar issues >> with smc_* macros on armv6. >> >> I have attached a patch that reuses more of arm7 code for armv6. it >> looks like arm1176 uses virtually indexed caches, so it probably won't >> work. >> The other attached patch fixes PTs on arch with disabled caches. > > Hi Ján, > thanks for the detailed explanation. > > I've tried the changes that you suggest, but the result is always the > same. > > Unfortunately it's not easy to debug this kind of problem, so for now, > while I investigate further, the only way to have a working kernel is > to disable caches on armv6.
If you invalidate the entire data cache in cpu_arch_init() before the D-cache is re-enabled, the bug goes away. As the D-cache was never ever completely invalidated on AMRv6, I suspect that it still contained some valid entries that may have become incoherent with the memory (eg. memory used for stack). Btw, using the shareable attribute for the pages did not work for some reason with the STREX instruction. See #641 for more details: http://trac.helenos.org/ticket/641 Here is my working version of the fix: http://bazaar.launchpad.net/~jakub/helenos/arm/revision/2391 Best, Jakub _______________________________________________ HelenOS-devel mailing list [email protected] http://lists.modry.cz/listinfo/helenos-devel
