Hello, I have to use MSVC++ for a project because we failed to get Cygwin's (and MingW's) gcc to produce a stable executable. Anyway, being a (or trying to be, hehe) a command line oriented guy I decided to use MSVC++ from the command line as much as possible. I couldn't find a decent reference that would get me started using nmake quickly so I thought why not use gnu make instead? I wrote this simple Makefile for gnu make that uses cl (the MSVC++ compiler and linker). Here's the Makefile:
CXX = cl # /EHs: enable C++ EH (no SEH exceptions) # /nologo: disable banner (basically prints version information of compiler and linker) CXXFLAGS = /c /EHs /nologo LD = cl LDFLAGS = /link /nologo OBJECTS = foo.obj EXEC = foo.exe all: $(OBJECTS) $(LD) $(OBJECTS) $(LDFLAGS) /OUT:$(EXEC) %.obj: %.cpp $(CXX) $(CXXFLAGS) $@ $< clean: rm -f *.obj *.exe It seems to work just fine but there's one annoying problem. When it's compiling the .cpp-files to .obj-files, make sends this string to cl: cl /c /EHs /nologo foo.obj foo.cpp cl doesn't expect foo.obj to be there and ignores it and tells us about it: cl : Command line warning D4027 : source file 'foo.obj' ignored foo.cpp I would like to know how to get make to send the above string without foo.obj in it so I can get of the warning issued by cl. Thanks for any replies / Eric _______________________________________________ help-gnu-utils mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnu-utils
