%% Randy Yates <[EMAIL PROTECTED]> writes:
ry> It appears that there is a bug in gnumake that arises when a
ry> variable is redefined. For example, if I define "EXE = .a" in my
ry> main makefile, then specify a build rule for a target
ry> "myproject$(EXE)", then include a second makefile that redefines
ry> "EXE = .out" and makes some other build rules for other targets,
ry> then the first build rule seems to get confused. If I put "echo
ry> $(EXE)" I see the right value (".a"), but the target acts as if
ry> the second value (".exe") is present and the file does not
ry> recognize the command line target "myproject.a".
ry> Is this a bug? Is this a known bug?
If it behaves as you say (as best I can determine: examples are more
useful than textual descriptions) then it would be a bug. But, I cannot
reproduce this behavior myself. For example:
EXE = .x
foo$(EXE):
@echo EXE = $(EXE)
@echo @ = $@
EXE = .y
foo$(EXE):
@echo EXE = $(EXE)
@echo @ = $@
Gives the expected result:
$ make foo.x
EXE = .y
@ = foo.x
$ make foo.y
EXE = .y
@ = foo.y
Maybe you can provide an example or more detail about your situation.
--
-------------------------------------------------------------------------------
Paul D. Smith <[EMAIL PROTECTED]> Find some GNU make tips at:
http://www.gnu.org http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad Scientist
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