On Thursday 29 November 2007, a r wrote: > causes following problems. > > storage element step control error:Cgs.Mn1.xgate 1e-12 > using Euler, disabling time step control
Don't worry about this unless you really care about the influence of the capacitor Cgs.Mn1.xgate. It is doing what you want. When you see something like "Cgs.Mn1,xgate" .. this refers to the capacitor "Cgs" that is inside the model of "Mn1". > With timestep of 0.1ns the simulation runs fine but the > numerical ringing is very visible. > > Any idea? It depends on what you want. Maybe ".option method=euler" will make it work. If this is a digital circuit, that's what to do. That is what the "fast spice" simulators do. Spice does some re-interpolation of results, that often hides this kind of problem. You still get incorrect results, but without any indication that there might be something wrong, _______________________________________________ Help-gnucap mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnucap
