Thank you for detailed response. On Dec 3, 2007 8:59 PM, al davis <[EMAIL PROTECTED]> wrote: > It's not as bad as it looks. > > In a development snapshot, sometimes there are warnings for > things that would be suppressed later. > > I do not have your models, so I am guessing here.
The models I am using were posted to the gnucap-dev list before: http://www.dattalo.com/spice/TSMC_025u_Mosis.txt (I have only changed level=49 to level=8 for evaluating bsim3 models). I wished I could try Gnucap with "real" production models but for this it would need to support at least expressions and including libraries with sections. Preferably also verilog-a models. > > > > LEVEL = 8 VERSION > > ^ ? bad parameter, ignored > > That is probably a bug. I need to see the ".model". > > > > > and then bunch of warnings: > > > > Warning: This model is BSIM3v3.3.0; you specified a wrong > > version number. > > What version did you specify? Maybe you don't want 330 .. That's right. This should be bsim310 version. > > [...] > > initial step rejected:Mp.xi1 > > new=1.87716e-12 old=1e-11 required=5e-12 > [...] Thank you for explanation. > You say it works .... No trap ringing??? In fact, it is still ringing if I use trap method with default options. However, dtmin=0.001 solves the problem for this circuit (for larger circuits higher values are enough). Defaults are not very suitable for simple logic or sampled circuits. Regarding your next email: > I need to reword that message. > > How would you like something of the form ... > =============== > C567: is too fast > Required step for accuracy: 5.58e-18 > Min step per option dtmin: 1e-15 > Using Euler for this device. > =============== I tried that simulation with dtmin=1e-30: storage element step control error:Mn.xi1 7.46722e-19 using Euler, disabling time step control Interesting. The results are fine, though. -r. _______________________________________________ Help-gnucap mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-gnucap
