al davis wrote:
What are the pos and neg terminal names in the built in
model?
For a capacitor (and most basic 2-terminal devices) "p" and "n",
as per the Verilog-AMS spec.
I tried a simulation and get a message about internal node 2 open even though I
have none of that name specified.
Here is some gnucap output I am confused by:
gnucap-verilog>list
module verilog_io (GND,OUT,IN);
// continuous assignments
// Package instantiations
capacitor #(.c( 1.25u)) C1 (.p(B),.n(GND));
inductor #(.l( 0.001)) L1 (.p(B),.n(OUT));
resistor #(.r( 1.K)) R1 (.p(IN),.n(B));
endmodule // verilog_io
gnucap-verilog>build
>VIN (IN GND) pulse(iv=0, pv=5, period=0.02, width=0.01)
>
gnucap-verilog>list
module verilog_io (GND,OUT,IN);
// continuous assignments
// Package instantiations
capacitor #(.c( 1.25u)) C1 (.p(B),.n(GND));
inductor #(.l( 0.001)) L1 (.p(B),.n(OUT));
resistor #(.r( 1.K)) R1 (.p(IN),.n(B));
endmodule // verilog_io
vsource #(pulse.iv( 0.), .pv( 5.), .delay(NA( 0.)), .rise(NA( 0.)), .fall(NA( 0.)), .width( 0.01), .period( 0.02)) VIN
(.p(IN),.n(GND));
gnucap-verilog>print tran v(nodes)
gnucap-verilog>tran 0 0.1 .001
#Time v(GND) v(IN) v(n) v(p)
open circuit: internal node 2
0. 140.52 145.52 0. 0.
0.001 140.52 145.52 0. 0.
0.002 140.52 145.52 0. 0.
0.003 140.52 145.52 0. 0.
John
--
Ecosensory Austin TX
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