Sorry, I didn't check the latest postings before sending
this question (although I did search the archives but gave up on finding
anything relevant). Jean Boucher seems to be after exactly the same thing, so
just cancel this question!
/Anna
Från: Anna Olsson
Skickat: den 8 september 2005 11:08
Till: '[email protected]'
Ämne: Get prerequisites from variable with name based on target name?I'm trying to do something like this:# BEGIN MakefileTargets = a ba_sources = a.cpp b.cpp
a_libs = bepa cepab_sources = c.cpp
b_libs = depalibs = $([EMAIL PROTECTED])
sources = $([EMAIL PROTECTED])all : $(Targets)$(Targets): % : $(%_libs)
@echo Target $@:@echo libs: $(libs)
@echo sources: $(sources)
@echo# build a lot of stuff here based on $(libs) and $(sources).PHONY: all $(Targets)# END MakefileCalling 'make' for this file will result in a correct listing of the sources and libs for each target. The problem is that the prerequisites for targets seem to be the value of the variable '%_libs' rather than the value of 'a_libs' for target 'a' or 'b_libs' for target 'b', which of course was intended.Is there any way of making the prereqs evaluate '%' and construct the variable name correctly before evaluating the variable?BTW, neither$(Targets): $(libs)nor$(Targets): % : $(libs)does the trick!Hoping for help!/Anna
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