On 2006-3-10 13:47 UTC, Matt England wrote: > > How can one conditionally run "-include" in a rule?
I don't see how you can: directives are processed when 'make' reads a makefile, before rules are considered. As you point out, this can be controlled by ifeq...endif. > MAKE_DFILES := 1 > ifeq ($(MAKECMDGOALS),clean) > MAKE_DFILES := 0 > endif > ifeq ($(MAKECMDGOALS),distclean) [...] > ifeq ($(MAKE_DFILES),1) > -include $(ALL_DFILES) > endif You could delegate almost all of the real work to a submakefile in which you include dependency files, and handle targets like 'clean' in the top-level makefile (which needn't include dependency files). Or you could do all the work in a submakefile, to which you'd pass a target-specific $(SRCS) (which could be empty for targets like 'clean'), and do this include $(SRCS:.cpp=.d) in the submakefile. That might be profitable if you have many targets with disjoint sets of source files. > I simply have to include ALL my .d > files (that map to a one-to-one basis with my .cpp files) for EVERY > application build, and undesirable situation (although the user can play > a little trickery on the cmdline to take out the other applications from > the app list with variable assignments, but this too is undesirable). It's not optimal, but the solution isn't pretty either. Do you have so many '.d' files that 'make clean' takes an inordinate amount of time? If so, can you refactor them into different directories? Or perhaps shorten them by using '-MMD' instead of '-MD', if you create them with gnu cpp? _______________________________________________ Help-make mailing list [email protected] http://lists.gnu.org/mailman/listinfo/help-make
