On Wed, Jun 11, 2008 at 12:03 AM, Timothy Reilly <[EMAIL PROTECTED]> wrote:
> I've got a program that I'd like to compile with varying sets of options.
> All of these options are completely independent, and the actual dependencies
> of the targets are the same- they differ only in options passed to the
> commands. My idea was to have each set of flags be a pattern match rule and
> an explicit rule. The pattern match rule would match the option-set to the
> suffix, strip the suffix, and depend on the prefix, which would repeat the
> process until only a single option-set remained, which would match the
> explicit rule. Here's the relevant portion of the makefile :
>
> debug: CXXFLAGS := $(CXXFLAGS) -Wall -g
> debug: all
>
> benchmark: CXXFLAGS := $(CXXFLAGS) -DBENCHMARK
> benchmark: all
...
> %_debug: CXXFLAGS := $(CXXFLAGS) -Wall -g
> %_debug: %
>
> %_benchmark: CXXFLAGS := $(CXXFLAGS) -DBENCHMARK
> %_benchmark: %
...
> The idea was to be able to do something as such:
>
> make vector_debug_openmp_benchmark
>
> and have CXXFLAGS expand to all of the relevant flags.
>
> The pattern match rules do not do what I'd like them to do, and I do not
> understand why. Is what I'm trying to do feasible/possible?
Yes, it's feasible. Indeed, you're very, very close.
1) a pattern rule without commands does not _define_ a pattern rule, but rather
_cancels_ it. So, if you want a pattern rule that does nothing,
give it an empty
command by appending a semicolon:
%_debug: % ;
2) when make finds a target-specific variable assignment (= or :=, but not +=),
it ignores any assignments for that variable that were previously in effect.
That's true even if the new one is a simple assignment (:=) that references
the variable in the new value! If you want multiple target-specific changes
to apply, you can only use append (+=)
So, combining those:
$ cat Makefile
var := base
all: var += all
all:
@echo ${var}
%_foo: % ;
%_foo: var += foo
%_bar: % ;
%_bar: var += bar
$ make all_bar_foo
base foo bar all
$
Philip Guenther
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