OK, you are right, I tried to simplify my question to make it shorter, but I
see it's not getting me anywhere.
I'm using make to build a Palm OS project.
Here's a (less) simplified version of my makefile:
cpps=$(wildcard *.c) $(wildcard Forms/*.c)
objs=$(cpps:%.c=%.o)
headers=$(wildcard *.h) $(wildcard Forms/*.h)
release-project: cflags = -c -o
release-project: ${objs}
m68k-palmos-gcc $^ -o $@
debug-project: cflags = -g -c -o
debug-project: ${objs}
m68k-palmos-gcc -g $^ -o $@
%.o: %.c $(headers)
m68k-palmos-gcc ${cflags} $@ $<
I'm using $(headers) so any change to a header file will recompile
everything. And yes, I know these are not cpp's, but I named it like that
because they will be in the future.
Now, I have about 50 source files in the main directory and in /Forms
When I want to build both release and debug I have to build release, clean,
and then build debug, because I have to get rid of all the O files.
The ultimate solution is to have a Visual Studio type of structure where all
the release objs will go to /bin/release and all of the debug objs will go
to /bin/debug
But how can I make it so 'make' can compile incrementally with these obj
dirs?
Thanks.
On Mon, May 4, 2009 at 3:21 AM, Philip Guenther <[email protected]> wrote:
> On Sun, May 3, 2009 at 11:25 AM, t-timmy <[email protected]> wrote:
> > I want to name each of my object files prefixed with the current target
> > name. That way when I change targets, I won't have to recompile
> everything to
> > make sure there is no residue from the previous compilation (which may
> have been
> > for a different target).
> >
> > For example:
> >
> > target1: c_flags = -DSOMETHING
> > target1: main.o
> >
> > target2: c_flags = -DSOMETHING_ELSE
> > target2: main.o
> >
> > main.o:
> > gcc $(c_flags) etc...
>
> No, that isn't an example of what you want, because that doesn't use
> prefixes like you want. As is, you didn't give us enough to go on.
> You don't show any rules for linking programs, so saying "make
> target1" will compile main.o but *not* create a program from it, which
> is almost certainly not what you want, but we can't tell whether "make
> target1" should build a program "target1" from main.o or whether it
> should build "target1-someprogram" from main.o
>
> Next, you show main.o with an explicit rule. Really? You give each
> .o an explicit rule instead of using pattern rules? Why? If you
> actually have a real reason to do that (how can we tell?) then that'll
> affect what solutions are appropriate.
>
>
> > The only way I can avoid recompiling every time is by manually making a
> rule
> > for, let's say, target1-main.o and target2-main.o, but I have a lot of
> > source files and it's a real hassle.
>
> Make give you at least two different ways to let you use the same rule
> for the two targets. You almost certainly only one of the following;
> you'll need to decide which though the former is probably simpler.
>
> 1) target-specific variable assignments. As described in the info
> pages, such a setting
> is propagated to all the prerequisites of the target, so setting
> CFLAGS for target1
> will mean that it'll be set for the files target1 depends
> on...which would presumably
> be things like target1-main.o
>
> 2) automatic variables. These are the variables like $@ and $^ that
> are set for you
> by make with values that depend on the rule involved. You can use
> the same rule
> for both target1-main.o and target2-main.o and example $@ in the commands
> to
> figure out which settings to use.
>
>
> Philip Guenther
>
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