Hi all,
I need to write makefile for my project. I wrote some basic makefiles, and
never used automatic variables. But the makefile that my project needs is a
bit more complex (has to be recursive and few other stuff). I'm learning how
to write such makefiles. While learning I came across the automatic
variables and tried them on a simple code (file name: test.c).... I wrote
the following makefile:
EXEC = test
OBJS = test.o
all : $(EXEC)
$(EXEC) : $(OBJS)
% : %.o
echo "First line\n"
gcc $< -o $@
# %.o : %.c
# echo "This is second line\n"
# gcc -c $<
.PHONY : clean
clean :
-rm -f $(EXEC) $(OBJS)
With the lines that are commented I'm not providing any rule to make the
object files. Hence when I execute make I expected this to give me error,
but this proceeds smoothly with following output:
cc -c -o test.o test.c
echo "First line\n"
First line\n
gcc test.o -o test
does make "know" howto get .o files even with out specifying. Why doesn't
this give me an error as I expected.
Thanks.
-----
"tron"ix
--
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