I'm afraid make is not very suited to do what you want. I don't think make is designed to understand you want to build and include iteratively in sequence, using immediately the variables that have been set inside the generated makefiles, while building the other makefiles. Though I think it'd be nice if it did...
Make will identify the included makefiles as targets that will have to be built if they don't exist yet. It will also build them in sequence, but in the same (pre)run. So it will build FILE_A and FILE_B together in the first run, then execute a second run, include both and run the actual target called. However, since it is building both include files during the first run, it doesn't bother to include FILE_A in between building FILE_A and FILE_B again. I suppose you could do this: makefile: include FILE_B > include FILE_A > > default : > @echo TEST_A = $(TEST_A) > @echo TEST_B = $(TEST_B) > > FILE_A : > $(MAKE) -f makefile.includes $@ > > FILE_B : FILE_A > $(MAKE) -f makefile.includes $@ > > clean : > @rm -rf FILE_* makefile.includes: include FILE_A > > FILE_A : > echo "TEST_A = 1" > $@ > > FILE_B : FILE_A > echo "TEST_B = $(TEST_A)" > $@ Make sure you DON'T include FILE_B in makefile.includes. If you do, it will again try and create both FILE_A and FILE_B during the recursive call for FILE_A, and again you have the wrong FILE_B which now exists, preventing the main thread to try and recurse again and build FILE_B. -- View this message in context: http://old.nabble.com/how-to-write-such-dependence---tp32273848p32310285.html Sent from the Gnu - Make - Help mailing list archive at Nabble.com. _______________________________________________ Help-make mailing list [email protected] https://lists.gnu.org/mailman/listinfo/help-make
