In Microsoft NMake, you can use $* to refer to the current target's path and basename:
EmployeeTest.exe: $*.obj Employee.obj $(CPP) $(CPPFLAGS) $** /Fe$@ ($** in the recipe then refers to the list of dependents of the current target. And CPP/CPPFLAGS in Nmake refer to the C++ compiler, not the C preprocessor.) http://msdn.microsoft.com/en-us/library/cbes8ded.aspx How can you refer to the current target't basename and path in GNU Make? EmployeeTest.exe: EmployeeTest.o Employee.o $(LINK.cc) $^ -o $@ DatabaseTest.exe: DatabaseTest.o Employee.o Database.o $(LINK.cc) $^ -o $@ EmployeeTest and DatabaseTest are redundant here, how can you avoid that redundancy in specifying the rule? -- Michael Ludwig _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make