On Mon, 2012-06-11 at 23:53 -0400, ogronom wrote: > # --------BEGIN > tests_SRC=1.c 2.c > tests=$(tests_SRC:.c=.out)) > > define out_template = > $(DEST_DIR)/$$($(1):.c=.out) : $(1) > echo $$@ $(1) > endef > > $(eval $(call $(out_template 1.c))) > $(eval $(call $(out_template 2.c))) > > all: $(tests) > > check: $(tests) > for f in $(tests) ; do ./$$f ; done > #---------END
First, you should put "all" closer to the top. It should be the first target defined. > make: *** No rule to make target `1.out', needed by `all'. Stop. Your invocation of the $(call ...) function is wrong, first of all. It should be: $(eval $(call out_template,1.c)) $(eval $(call out_template,2.c)) The first argument to the call function is expanded and the expansion is treated as the name of a variable to be used as the user-defined function. The remaining arguments are used to replace $1, $2, etc. In your case, where you write $(call $(out_template 1.c)), make evaluates the reference $(out_template 1.c); since there's no variable by that name it evaluates to empty, which means you're invoking $(eval ) (on the empty string) and nothing is being defined. If you replace $(eval ...) with $(info ...) you'll see what make is evaluating; that can be a useful debugging tool. Running make with --warn-undefined-variables would have also helped, but note that gives a lot of false positives as well. _______________________________________________ Help-make mailing list Help-make@gnu.org https://lists.gnu.org/mailman/listinfo/help-make