Hi all,
I have tuned my Makefile for automatic dependencies generation and it
looks like this
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
OBJDIR := objs/
OBJS := $(SRCS:%.cpp=$(OBJDIR)%.o)
DEPDIR := $(OBJDIR)
DEPS := $(SRCS:%.cpp=$(DEPDIR)%.d)
TARGET := prog
# Default target
$(TARGET): $(OBJS)
$(LD) $(LDFLAGS) -o $@ $^
$(OBJDIR)%.o: %.cpp
test -d $(OBJDIR) || mkdir -p $(OBJDIR)
$(CXX) $(CXXFLAGS) -c $< -o $@
$(DEPDIR)%.d: %.cpp
test -d $(DEPDIR) || mkdir -p $(DEPDIR)
$(CXX) $(CXXFLAGS) $< -MM -MG -MP -MT '$(OBJDIR)$*.o' -MF $@
clean:
rm -f $(TARGET)
rm -rf $(OBJDIR) $(DEPDIR)
-include $(DEPS)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
My problem is that every time that I run make clean, the rules for
creating DEPS are executed again.
Is there any way to tell the Makefile to ignore the final include line
(or empty the DEPS var) when I run make clean?
In my case I need the .d files before I generate the .o ones since I
use generated files from flex/bison and I need to respect the
dependencies.
Please CC me in your replies, since I am not subscribed in the list
Thanks a lot in advance,
Nick
--
=Do-
N.AND
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