Hello,
I've noticed multiple ways of including a Makefile within another Makefile.
For example, one could directly include the Makefile:
# Filename top.mk
...
include /path/to/file.mk
One could also use the $eval function to include the Makefile:
# Filename: top.mk
...
$(eval include /path/to/file.mk)
Both work fine. What's the difference? Is there an optimal or preferred
method?
Thanks!
Hiran
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