To translate what your command is "saying" to make:
make -f myfile.mk trlfn
equates to "read myfile.mk and then execute the recipe to produce the
target trlfn".
But trlfn is not a target because it has no recipe.
> Would there be no prerequisites for such cases?
Prerequisites are targets that need to be resolved before building the
desired targets. They are not dynamic bits of code like in your example.
> If I want to build my program with gcc, I might need to set compiler
options by specifying what I want to the makefile. How would it be a
wrong idea?
That's an entirely separate topic. You typically set compiler flags with
an environment variable. NOT with a target (.PHONY or otherwise)
I also slightly misread your makefile because it's so off-syntax:
trlfn: hopc += --transliterate-file-names
This makes even less sense than I thought - if hopc is your executable,
you cannot "add to it" with +=, which is an extension to an existing
variable (although it might work slightly by accidend by just assuming
that "hopc" is a string that you then append to)
The target shape that you want could be something like
# myfile.mk
hopc-result.trlfn:
hopc --transliterate-file-names
hopc-result.ndf:
hopc --node-files
hopc-result.trlfn.ndf:
hopc --transliterate-file-names --node-files
and then call it via
make -f myfile.mk hopc-result.trlfn
but that's overly contrived.
Anyhow - maybe what you're actually looking for here IS an environment
variable?
> I do not think I am using wrong tool for the job.
You're using make like a bash script. That's not inherently wrong, but
what Make really wants to do is resolve dependency graphs to build
targets via their recipes.
-David
On 6/22/26 23:05, Heime wrote:
On Tuesday, June 23rd, 2026 at 8:45 AM, David Deutsch <[email protected]> wrote:
Like in your other mail - you're trying to go against a fundamental
concept in make.
A target is a target. What you're telling make with:
make -f myfile.mk trlfn #(or ndf)
is "I want target myfile.mk to be one thing if I also tell you to
build trlfn and another thing if I tell you to also build ndf and YET
another thing if I tell it to also build trlfn and ndf at the same time".
That means your Makefile has - in your theory - four separate
understandings of what myfile.mk fundamentally is.
If you keep pursuing this route, you're going to have a bad time because
make works best when targets have clear and final meanings.
The reason why trlfn/ndf does not work is because you have not provided
a recipe to it, in two different ways: First, you thought a recipe was
"the thing that make executes when I tell it to make a target" - which
is kind of true, but not for makefile syntax which is evaluated before
recipes are built (but in this case, will be ignored). Second: You just
wrote the recipe behind the colon. That's where the prerequisites go.
The actual recipe goes into the next line after a tab.
Would there be no prerequisites for such cases?
I would think that you're looking for outside variables, but from your
other email, you already seem to know about those.
What you're actually seem to be trying to do is use makefiles as though
they were a bash script. Wrong tool for the job.
-David
I do not think I am using wrong tool for the job. If I want
to build my program with gcc, I might need to set compiler
options by specifying what I want to the makefile. How would
it be a wrong idea?
On 6/22/26 22:04, Heime wrote:
How can I have targets that append values to variables?
Doing as follows produces error on hopc.
.PHONY: trlfn ndf
trlfn: hopc += --transliterate-file-names
ndf: hopc += --node-files
What I want is that calling
make -f myfile.mk trlfn
will append --transliterate-file-names to hopc
