Bill Fairchild wrote:
In a message dated 7/13/2005 8:35:47 P.M. Central Daylight Time,
[EMAIL PROTECTED] writes:
Wouldn't XR R15,R15 have been more efficient?
No. Yes. On what processor?
Even in the S/360 days the answer would depend on the box. Likewise SR
versus SLR vs LA.
Right on, Shmuel.
I learned Assembler's op codes on a S/360 model 30. I still prefer to do a
SLR to clear a register over SR and XR because SLR was the fastest way on the
model 30. But on today's big-end processors, the time to execute any one
given instruction depends on 853 variables, give or take πr². But the real
bottom line is that the difference in how long it takes any of the different
possible ways is vanishingly minute, and only of practical value if that
instruction must be executed thousands of times per second. The amount of time it
takes a programmer to think about which of three different instructions to use
costs millions of times more than the cost recovered by executing the
optimal instruction.
However, even though it is not of much value, it is certainly of interest.
If you really want to know how to speed instructions up, you must be prepared
to read lots of highly arcane technical papers on instruction processing
units, pipelines, instruction caches, translation lookaside buffers, data
caches, bus width, look-ahead instruction preprocessing, multiple processor
serialization effects, instruction predecessor relationships, et alia. That's where
the 853 variables comes from. The model 30 had a simple set of numbers with
no variables. Load Address was something like 19 microseconds no matter
what.
Not quite, IIRC if the index register is not zero then add a few
microseconds for any instruction with index reg.
Bill Fairchild
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