Shmuel Metz , Seymour J. wrote: > Wasn't that already true on the older 360/85?
i did some work with a 165/168 processor engineer ... he said that one of the things for the 165->168 transition was that they reduced the avg. machine cycle time per instruction from avg 2.1 machine cycles to 1.6 machine cycles (besides 168 having faster memory and misc other things). the 3033 started out being 168 wiring/logic diagram mapped to chip technology that was about 20percent faster and having about ten times the circuits per chip (but originally additional circuits unused). late in the process, there was work on optimizing 3033 logic to better utilize the additional circuits (increase on-chip operation) ... which eventually resulted in 3033 shipped to customers being about 50percent faster than 168. there was some mvs kernel performance assist microcode done for 3033 ... somewhat analogous to vm ecps originally done on 148 ... but it was difficult to actually demonstrate much performance improvement because 370 instructions already running at or close to hardware speed. sie instruction was introduced for 370/xa with 3081 .. but still required the vm kernel. there was vm assist introduced on 158 & 168 ... which still used normal 370 instructions to switch from kernel to virtual machine mode. vm ran the virtual machine in problem mode and all supervisor state instructions interrupted back into the kernel. the vm assist had pointer loaded into control register 6 (otherwise unused). now some supervisor instructions ... when running in problem mode ... would first check cr6, and instead of interrupting into the kernel would execute according to "virtual machine" architecture rules (rather than real machine architecture rules). ecps done for the 148 ... besides moving pieces of the kernel into native microcode ... also added additional supervisor instructions that would execute under virtual machine architecture rules. sie instruction, intorduced for 370/xa on 3081 ... replaced the whole mechanism switching from vm kernel to virtual machine mode (and back) as well as providing indications to the hardware that the machine was running in "virtual machine" mode. Essentially, it created three machine modes, supervisor state, problem state, and virtual machine supervisor state. note, however, the sie instruction still required vm kernel to operate. amdahl hypervisor effectively ran operating system somewhat akin to current lpar ... w/o requiring vm kernel to handle various functions ... effectively enuf of the vm kernel functions had been moved into the hardware (in this case, macrocode) that a vm kernel wasn't required to run in hypervisor mode. there are two issues here: 1) straight-line replacement of kernel instructions with kernel microcode ... this provides performance boost if the native machine speed is much faster than the 370 speed (i.e. collapsing high number of microcode instructions per 370 instruction into single microcode instruction). this sees much less benefit if 370 instructions are running at nearly hardware speed. 2) elimination of state change, register saving/restoring, etc ... switching back and forth between kernel mode and virtual machine for supervisor instruction simulation. if there is a 3rd mode where supervisor instructions are directly executed according to virtual machine architecture supervisor state rules (rather than real machine supervisor state rules). the amdahl macrocode mode made it easier to do write the programming for hardware virtual machine mode ... implementing hypervisor. there is significant savings in operations needed to be performed ... even on machines where 370 instructions run at hardware speed. misc. past postings mentioning macrodoe http://www.garlic.com/~lynn/2002p.html#44 Linux paging http://www.garlic.com/~lynn/2002p.html#48 Linux paging http://www.garlic.com/~lynn/2003.html#9 Mainframe System Programmer/Administrator market demand? http://www.garlic.com/~lynn/2003.html#56 Wild hardware idea http://www.garlic.com/~lynn/2005d.html#59 Misuse of word "microcode" http://www.garlic.com/~lynn/2005d.html#60 Misuse of word "microcode" http://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned programming language http://www.garlic.com/~lynn/2005p.html#14 Multicores http://www.garlic.com/~lynn/2005p.html#29 Documentation for the New Instructions for the z9 Processor http://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries? misc. past posts mentiong 165, 168, etc machine cycle http://www.garlic.com/~lynn/2000d.html#61 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition) http://www.garlic.com/~lynn/2000d.html#82 "all-out" vs less aggressive designs (was: Re: 36 to 32 bit transition) http://www.garlic.com/~lynn/2000e.html#54 VLIW at IBM Research http://www.garlic.com/~lynn/2000g.html#7 360/370 instruction cycle time http://www.garlic.com/~lynn/2001c.html#1 Z/90, S/390, 370/ESA (slightly off topic) http://www.garlic.com/~lynn/2001h.html#69 Very CISC Instuctions (Was: why the machine word size ...) http://www.garlic.com/~lynn/2002.html#48 Microcode? http://www.garlic.com/~lynn/2002e.html#18 Opinion on smartcard security requested http://www.garlic.com/~lynn/2002e.html#36 Crypting with Fingerprints ? http://www.garlic.com/~lynn/2002l.html#2 What is microcode? http://www.garlic.com/~lynn/2002m.html#68 Tweaking old computers? http://www.garlic.com/~lynn/2002m.html#75 New Book http://www.garlic.com/~lynn/2002n.html#23 Tweaking old computers? http://www.garlic.com/~lynn/2002n.html#58 IBM S/370-168, 195, and 3033 http://www.garlic.com/~lynn/2002p.html#44 Linux paging http://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions http://www.garlic.com/~lynn/2003m.html#37 S/360 undocumented instructions? http://www.garlic.com/~lynn/2005e.html#59 System/360; Hardwired vs. Microcoded http://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned programming language http://www.garlic.com/~lynn/2005p.html#29 Documentation for the New Instructions for the z9 Processor http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist http://www.garlic.com/~lynn/95.html#3 What is an IBM 137/148 ??? http://www.garlic.com/~lynn/96.html#23 Old IBM's http://www.garlic.com/~lynn/99.html#116 IBM S/360 microcode (was Re: CPU taxonomy (misunderstood RISC)) ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
