> Just out of curiousity, why is the zSeries CPU so poor at CPU-intensive > workloads, like Java? Is it the "clock speed" of the circuitry? Is it > the complexity of the instructions? Is it the fact that the machine does > a lot of internal checking / checkpointing for reliability and recovery?
Well first of all, I would NOT say that performance is poor. Its just not as good on certain types of workload and also tends to run at a lower clock rate than some other machines. There are quite a few reasons, rather than just one single one. The biggie IMO is that z architecture is demonically complex to implement in silicon. For a given clock rate and instruction architecture, the performance of a cpu is fairly predictable - at least analytically. So the faster you can clock it the faster it will execute instructions - all else being equal. Also, for a given fab technology there is a theoretical upper limit on the clock rate. Design complexity lowers the rate that can be achieved. Z architecture ends up needing lots of gates and logic levels and ultimately limits the clock frequency. The memory model is also more complex, but then again people tend to expect reliability rather than speed when they are messing with bank balances. There's not a lot of point clocking the cpu faster than it can eat data, so to a large extent the cpu is gated by the cache and memory subsystem design. There are also significant performance differences and design trade-offs based on the different workload mixes expected by the customer base. Z architecture favors on-chip cache area over raw clock speed. The basis of that idea is that when you run a general purpose mixed workload, you will do a lot of context switching and less raw computing. The POWER RISC guys make a different trade off to get more raw performance. So if you want to run a bomb simulation, you're better off running it on a pSeries. If you want lots of address spaces running lots of independent transactions the z may well be the better performer, even on a per-engine basis! Millicode is (among other things) an effort to improve the speed/area trade-off by removing logic from the silicon and replacing it with what is effectively software. That moves the z design closer to the POWER concept and I am guessing that trend will continue and the clock rates will get closer to their technology limits. BTW> the POWER RISC designers and the z designers are the same people. They flip-flop between hardware platforms for each generation of processor technology. Technology leadership swaps back and forth between z and p. The z9 is the more recent, and probably the technology leader (for now) In raw compute power the pSeries will still win, but the z has a more balanced overall design for mixed workload throughput. CC ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
