Leif Rundberget (as quoted by Joel C. Ewing) wrote:
| Be careful with like terms between the PC(intel) world and the mainframe
| world. When someone says they have a 64-bit Intel server (Intel,
| Solaris, AMD, etc.), it does not mean that the server can access an
| address 64-bits long, the 64-bits refers to the width of the bus. So it
| can transfer 64-bits in parallel.
There is once widely used IBM terminology for this quantity. As far back as
the System/360, a model 30 had a FETCH WIDTH of one eight-bit byte and the
fastest models, as they came along, had fetch widths of eight bytes.
Higher fetch width is "good", but it can have odd side effects. There were
System/360 models for which Load Halfword (LH) was slower than Load (L) not
just because of sign propagation but also because LH fetched four or eight
bytes from storage two or six of which then had to be discarded.
Analogously, there are z/Architecture situations in which eight-byte
(64-bit) instructions are faster than their four-byte (32-bit) variants.
John Gilmore
Ashland, MA 01721-1817
USA
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