Gerhard Postpischil wrote:
Steve Comstock wrote:
Then I issue OPEN against that ACB: I get S0C4 that
points to the next instruction after my OPEN, which
is an LTR 15,15; so it looks like the abend is being
generated in OPEN.
open ((10)),mode=31,mf=(e,openlist)
To eliminate one more "obvious" possibility - is openlist initialized,
i.e., is the x'80' end of list bit on?
Gerhard Postpischil
Hmmm. Interesting question.
Openlist is defined in my DSECT area:
openlist open 0,mode=31,mf=l
+OPENLIST DC 0F'0'
+ DC AL1(128)
+ DC AL3(0)
+ DC A(0)
So the x'80' bit is on here, but since it's in a DSECT,
of course, no real initialization occurs. The code where
the OPEN is invoked shows on the listing as:
open ((10)),mode=31,mf=(e,openlist)
+ LA 1,OPENLIST
+ ST 10,4(1,0)
+ LR 0,1
+ SR 1,1
+ SVC 19
ltr 15,15
So, no, I would say the x'80' bit is not on at
execution time. But, it is not clear how one
would do that (without manually coding the
macro expansion oneself). The doc does not
include the classic 'vl' operand as an option:
[label] OPEN (address[, [(options)][,...]])[,MODE={24|31}]
Hmmm.... no, not sure what to do about that.
Anyone have any thoughts?
Kind regards,
-Steve Comstock
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