The following message is a courtesy copy of an article that has been posted to bit.listserv.ibm-main,alt.folklore.computers as well.
[EMAIL PROTECTED] (Jim Mulder) writes: > But actually it did not take decades, as the original release of > MVS/XA in 1982 functionally supported 16-way SMP. Of course there > were no such processors at the time (nothing greater than 2-way until > the 4-way 3084), but it did run for testing purposes using 16 virtual > CPUs on a modified version of VM. Of course, as larger processors > were actually built, additional was done (and continues to be done) > to address performance/scaling issues. re: http://www.garlic.com/~lynn/2007t.html#76 T3 Sues IBM To Break its Mainframe Monopoly well, sort of. one of the things to get rapidly to 16-way smp implementation, as well as addressing performance/scaling issues, was to relax standard 370 cache consistency rules (and, in fact, most SMP vendors going to larger numbers of processors have almost always involved how to deal with cache consistency issues). remember that compare&swap ... misc. posts about smp and/or compare&swap http://www.garlic.com/~lynn/subtopic.html#smp was invented by charlie (compare-and-swap was chosen because CAS are charlie's initials) at the science center http://www.garlic.com/~lynn/subtopic.html#545tech and i've mentioned before the original difficulty of getting compare-and-swap into 370 architecture. Some of the difficulties is why the example of program failure still appears in the compare-and-swap writeup http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DZ9ZR003/A.6.1?SHELF=DZ9ZBK03&DT=20040504121320 i've frequently claimed that the 801 risc effort http://www.garlic.com/~lynn/subtopic.html#801 was attempt to go to the opposite extreme from what went on in FS http://www.garlic.com/~lynn/subtopic.html#futuresys and also claimed the lack of cache consistency in 801 risc was adverse reaction to the heavy performance penalty paid in 370 by its strong cache consistency requirement. in fact, it wasn't until somerset (joint ibm, motorola, apple, et all) for power/pc that there was (risc) work on smp and addressing cache consistency. in any case, part of doing 16-way smp (and relaxing 370 cache consistency rules) was much more detailed attention paid to every piece of code (because of the associated hardware changes for relaxed cache consistency). for some more topic drift, in just the 3084 time-frame, both mvs and (standard) vm had effort to go thru all kernel data & storage management and make sure things were cache-line sensitised. the issue was the increased probability that more than one cache might be accessing different data items which happened to overlap in the same cache line (resulting in significant cache line thrashing). The claim at the time was that this effort resulted in 5-10 percent increased system thruput (for 4-way). As the number of independent caches that had to be coordinated ... the probability increases that there is going to be some kind of cache interference. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [EMAIL PROTECTED] with the message: GET IBM-MAIN INFO Search the archives at http://bama.ua.edu/archives/ibm-main.html
