Someone wrote:

>>Assuming DAT on, is the performance hit related to the possibility
>> that the following 4096 page is not in virtual memory?

Lynn Wheeler wrote:

> way back on 360/67 ... (actually all 360s) TR used to test start &
> start+255 (end) address of the table ... which met that if it
> crossed a 4k page ... it would catch both ... aka page fault both
> pages ... before starting instruction execution.

For S/360 models with DAT.

> somewhere along the way ... something was raised that TR only
> uses that much of the table that the input data-stream might
> used ... for instance, if the translation input stream only
> had values 0-9 ... and the table was within 256 bytes of the
> end of an addressable region  ... then the instruction might
> fail (with start+256 precheck) ... even tho it otherwise could
> succesfully execute. so the TR instruction was
> "fixed" ... if the table start is within 256 bytes of the end
>  of an addressable boundary... it "pre-executes" the instruction
>  to see if any input stream bytes would index the table
> across the boundary.

S/360 GA22-6821-8 in the paragraph about logical operations
at the beginning of the chapter and describing TR says:

  "In cases where it is known that not all eight-bit argument
  values  will occur, it may be possible to shorten the list."

> this would also theoritically have been a problem with 2k key fetch
> protect ... and the table was within 256 bytes of a 2k boundary (with
> the next 2k, fetch protected) and the input data stream never indexed
> anything (in the table) across the addressable boundary.

It seems like it would also be a problem on non-DAT machines at
4K boundaries.   It does seem to have been added fairly late
in S/370, though.  (At least when it got documented.)

I first learned about this in Nick Tredennick's book "Microprocessor
Logic Design" about the Micro/370.

http://en.wikipedia.org/wiki/Nick_Tredennick

-- glen

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