If some particular instruction set feature is installed, the
definition of ASI/AGSI is enhanced to serialize the update, making it
a simpler solution than a CDS loop or PLO.
In some performance testing a while back on a z14 or z15 which I think
had the above serialization feature, the execution times for a very
large number of executions of L / AHI / ST were very close to the same
count of ASI. If I recall, the ASI was a few percent slower, I guess
because of the serialization. I.e., unless you're doing abnormal
tests as I did, you won't notice the difference.
/Leonard
Seymour J Metz wrote on 3/1/2023 1:33 PM:
In addition to the obvious instructions Phil mentioned, there is also PLO. I
don't have any relevant performance data.
--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3
________________________________________
From: IBM Mainframe Discussion List [IBM-MAIN@LISTSERV.UA.EDU] on behalf of
Ituriel do Neto [000003427ec2837d-dmarc-requ...@listserv.ua.edu]
Sent: Wednesday, March 1, 2023 3:52 PM
To: IBM-MAIN@LISTSERV.UA.EDU
Subject: CS/CDS instruction
Hi all,
Is there a similar instruction to CS or CDS, but using 64 bits register ?
I have a double word that contains a counter and using 64 bits instructions
would be faster to increment this value than manipulate it with other storage
areas and an even-odd pair of 32 bits registers.
Thanks in advance
Best Regards
Ituriel do Nascimento Neto
z/OS System Programmer
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