Tim,

Thanks for the link.  While the initial discussion, from that link, seemed a 
little light on some of the details, I found a very good article, that seems to 
dive into the guts of the new TELUM II processor and Spyre card.

https://www.servethehome.com/ibm-telum-ii-processor-and-spyre-ai-updates-at-hot-chips-2024/

A few of the other articles I read, concentrate on the enhancements on the 
Telum II related to cache size, and specifically the AI accelerator 
performance, however the DPU has seemed to be glossed over.  I would put it out 
there, that those authors may not understand the Z platform and how it does 
things, internally (and yes, this has been discussed ad nauseum over the years 
- so no need to go into that arena again, please).

This article (above) seems to discuss it more, and it's very interesting.  If I 
am reading it correctly, is the DPU bringing, onto the Telum II processor chip, 
many of the functions, that we normally associate with the I/O subsystem?  It 
talks about a reduction in power usage by 70% in I/O handling, and direct 
access to the PCIe slots, so I am inferring, in my mind, that it is doing 
exactly that.  Very cool.

Also, nice to see that the core speed, of the full speed processor is going 
from 5.2 Ghz on the Telum up to 5.5 Ghz on the Telum II.

Overall, very cool improvements to the Z family processor.

Peter

On Tue, 27 Aug 2024 08:15:27 +0000, Timothy Sipples <sipp...@sg.ibm.com> wrote:

>IBM presented many details about the IBM Telum? II Processor (with a 
>completely new Data Processing Unit) and IBM Spyre? Accelerator yesterday at 
>the Hot Chips 2024 conference.
>
>https://newsroom.ibm.com/ai-on-z
>
>?????
>Timothy Sipples
>Senior Architect
>Digital Assets, Industry Solutions, and Cybersecurity
>IBM Z/LinuxONE, Asia-Pacific
>sipp...@sg.ibm.com
>
>
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