Unless the target of the branch is in protected storage. That would allow a
ghost type attack.

On Sat, 3 May 2025 17:40:48 +0000 Seymour J Metz <[email protected]> wrote:

:>To locate the failing instruction, look at both IC and ILC. It all works as 
documented.
:>
:>IIC?
:>
:>-- 
:>Shmuel (Seymour J.) Metz
:>http://mason.gmu.edu/~smetz3
:>??? ?????????? ???
:>?????? ??????????? ???? ??????????
:>
:>
:>
:>________________________________________
:>From: IBM Mainframe Discussion List on behalf of Johnny Luo
:>Sent: Friday, May 2, 2025 11:02 PM
:>To: [email protected]
:>Subject: Two different types of 0cx abend
:>
:>
:>External Message: Use Caution
:>
:>
:>Hi,
:>
:>When you execute a "br 14" and r14 contains an invalid address, "br 14"
:>will be successfully executed (and will be recorded in BEAR)  and the
:>content of r14 will be loaded into PSW. Then an exception will occur while
:>fetching the next instruction.
:>
:>So in my understanding, an ocx could occur at fetch&decode stage  as well
:>as the execution stage. In the former the psw points to the failing
:>instruction. In the latter the psw point to the next instruction, so IlC
:>should be used to get the address of the failing instruction.
:>
:>Is there something wrong with my above thoughts?
:>
:>Thanks.
:>
:>Best Regards,
:>Johnny Luo
:>
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:>
:>
:>
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--
Binyamin Dissen <[email protected]>
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel

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