[email protected] (John Gilmore) writes: > Long-winded and ugly but functionally adequate serialization machinery > can be developed using TS alone
that was the argument that the POK favorite son operating system people used when attempt was made to add comapre-and-swap to 370. charlie had invented compare-and-swap while doing fine grain multiprocessing locking for cp67 at the cambridge science center. attempts to add it to 370 was met by opposition from the POK favorite son operating system (having used single TS spin-lock for entering os/360 360/65mp kernel). The owners of the 370 architecture then said in order to justify compare-and-swap for 370, non-multiprocessor use cases would be needed. thus was born the non-multiprocessor specific use cases that still appear in the principle of operations. TS use case was multiprocessor set a lock serizliation followed by some operation (critical section) followed by clearing the lock. compare-and-swap is single serialized non-interruptable, atomic operation. The compare-and-swap use cases include non-kernel, interruptable, multi-threaded (not necessarily multiprocessor) operation performing atomic serialized operations w/o the overhead of making kernel call to perform serialized operation. misc. past posts mentioning multiprocessing and/or compare-and-swap http://www.garlic.com/~lynn/subtopic.html#smp compare-and-swap was fairly quickly adopted by large multi-threaded applications like high throughput DBMS systems. compare-and-swap was so useful, numerous other hardware platforms adopted it also (or instructions with similar atomic semantics). ibm's 801/risc architecture was originally developed in the period around Future System (failed new machine architecture that was going to completely replace 360/370) ... and i've frequently claimed that there was a lot of 801 objectives to the extreme opposite of the FS complexity. One of the issues not to have cache consistency ... to avoid the enormous performance penalty paid by FS mutliprocessor (and even the extreme throughput penalty paid for 370 strong memory model multiprocessor cache consistency). misc. past posts mentioning future system http://www.garlic.com/~lynn/submain.html#futuresys No cache-consistency pretty much ruled out multiprocessor operation ... as well as philosophy of all instructions needed to complete in single cycle ... ruled out compare-and-swap instruction. however, the lack of compare-and-swap instruction ... put the RS/6000 at severe throughput disadvantage with open system RDBMS benchmarks compared to other platforms (open system RDBMS had fall-back to kernal call locking for few hardware platforms that didn't have compare-and-swap semantics). fairly early, compare-and-swap instruction emulation was added to the rs/6000 AIX system call FLIH ... within a couple instructions of entry to system call FLIH ... there was special case for compare-and-swap emulation that then immediately returned to application. While it wasn't useful for real multiprocessor operation, it did achieve the objective not being interruptable while emulation processing was in progress. misc. past posts mentioning 801/risc http://www.garlic.com/~lynn/subtopic.html#801 -- virtualization experience starting Jan1968, online at home since Mar1970 ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to [email protected] with the message: INFO IBM-MAIN
