On 12 November 2015 at 05:09, Nathan Astle <tcpipat...@gmail.com> wrote: > i got the below message in the HMC, > > Central processor (CP) 0 is looping due to switching between program status > words (PSWs) that are not valid. The program status word (PSW) is > 0000000000000000. > > The IPLTEXT was not written to the newly cloned RES Volume. Could that be a > reason ?
Yes. But there are many other possible causes; anything that overlays the program new PSW in low storage can provoke it. If another processor is available to z/OS it should be able to stop the loop, but not always. > I am not getting a correct explanation about x'000' on my search about the > above PSW in MVS manual codes. If it's not a wait-state PSW, there will be no wait state code present. More exactly, if it's not a disabled wait-state PSW, there is no wait state code documented in the MVS System Codes because this is not an error situation; it's just the system with no work to do. In this case of an enabled wait, the PSW address will usually be 0, though there is no architectural reason it couldn't be anything at all that the system wants to leave there.. In this case almost certainly the system is in that strange condition described in the Principles of Operation where the program new PSW is invalid (and subject to early detection). When this PSW is loaded as the result of a program interrupt, another (specification) program interrupt immediately becomes pending. This interrupt has a higher priority than almost anything else, and so hitting STOP or even RESTART will not stop the loop. I imagine that on modern machines the HMC warns when this situation occurs, just as VM has for decades. Tony H. ---------------------------------------------------------------------- For IBM-MAIN subscribe / signoff / archive access instructions, send email to lists...@listserv.ua.edu with the message: INFO IBM-MAIN
