Both Pause/Release and PC-ss are supported in SRB mode. The fact that you are in recovery code (and possibly unsure of the status of both ECB-owner and client) makes me believe that cross-memory POST is even more undesirable.
Not saying that it cannot be done with cross-memory POST, but Pause/Release offers more environmental validation prior to execution and encapsulating a PC-ss "POST" function isolates the recovery code from ECB-owner architecture and may allow recovery code to run problem state. As ever in the case of things like this, it is never what you *intend* to do that causes the problem...... -----Original Message----- From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> On Behalf Of Joseph Reichman Sent: Wednesday, September 26, 2018 1:23 PM To: IBM-MAIN@LISTSERV.UA.EDU Subject: Re: ECB in XMEM Post You are right as it kills all registers besides 9 If memory serves me right I think the for the system or PC call I know you are going to scream at me but the reason I choose the post is because I’m posting This from a recovery routine as I don’t know whether it’s TCB mode or SRB I’m using the system call I.E pc I am passing the SDWA storage area back in the 3 byte 24 bit comp code area The 3 byte comp code makes this convenient for me > On Sep 26, 2018, at 8:11 AM, Rob Scott <rsc...@rocketsoftware.com> wrote: > > Please be aware that cross-memory POSTs are not ideal and if possible I would > consider a redesign of your code to use other methods - for example : > > (1) Pause/Release > (2) PC-ss service into ECB-owner ASID to issue POST on caller behalf > > Just my 2c. > > Rob Scott > Rocket Software > > -----Original Message----- > From: IBM Mainframe Discussion List <IBM-MAIN@LISTSERV.UA.EDU> On Behalf Of > Joseph Reichman > Sent: Wednesday, September 26, 2018 1:01 PM > To: IBM-MAIN@LISTSERV.UA.EDU > Subject: Re: ECB in XMEM Post > > Sorry I misunderstood > So if Address Space A would like to post Address B the ECB must be > addressable to to B as that is the Target the ASCB is that of the target > Address space B the ECB can be B private area in A all I need is the address > of the ECB even in private and ASCB of B > > Thanks > > > On Sep 26, 2018, at 7:41 AM, Peter Relson <rel...@us.ibm.com> wrote: > >>> This is just another way of saying that for XMEM the ECB is in CSA >>> right >> ? >> No, not right. >> >> What within the wording "must be addressable from the address space >> identified by the ASCB parameter" makes you say that? Storage >> addressable from an address space includes common storage (whether CSA >> or SQA) and private storage of the address space. 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