(I wrote) >>VAX uses a two level system where page tables are paged. >>There is kernel space, which isn't paged and holds the first >>level tables referencing pagable second level tables.
>>z/Archtecture has three levels. (someone else wrote) > Actually, z/Architecture has 5 levels. So far, > the existed hardware only uses 3 of them. I thought of that right after sending it. Above the addressing within a page, it is, more or less, 10 bits per level. (For S/370, one could consider the 32 bit addressing for the 360/67, which is fairly similar.) For an undergrad operating system course I did a report comparing S/370 and VAX virtual memory systems (around the time when VAX was new). I remember finding more similarities than differences, especially both using the two level system. So for 64 bit addressing of 4K pages, (64-12)/10 is about five. Allowing the hardware to use three until more addressing bits are needed is a nice feature. -- glen
