On 2010.05.17 22:07:30 +0800, Li Peng wrote: > Pineview with DDR3 memory has different latencies to enable CxSR. > This patch updates CxSR latency table to add Pineview DDR3 latency > configuration. It also adds one flag "is_ddr3" for checking DDR3 > setting in MCHBAR. >
This is not against drm-intel-next? which has commit d4294342f to cleanup wm setup for pineview. -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827
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